Greetings from HACK Club!

Dates: 16-18 February 2021 - (session 1), 23-25 February 2021 - (session 2)
Venue: B-Block, 2^nd floor seminar hall.

As Moore’s Law slows down, there is increasing interest in the use of hardware accelerators, especially for ML / Big Data workloads. Examples include Google’s Tensor Processing Units and the recent Inferentia from Amazon. HACK club presents a 3-day workshop for getting started with hardware acceleration. The workshop aims to introduce you to an overview of hardware acceleration for ML / Big Data workloads, high-level design framework for hardware design and industry standard CAD tools for Intel FPGAs.

Agenda for the workshop:

• 16^th/23^rd February 2021
  • Introduction talk from Dr. Reetinder Sidhu.
  • Live demo of hardware acceleration.
  • Software setup and installations.
  • Short coding exercise in Verilog HDL.
  • Doubt clearing session.
• 17^th/24^th February 2021
  • Talk by Dr. Reetinder Sidhu on high-level design framework for hardware design.
  • Introduction to an in-house high-level design framework.
  • Doubt clearing session.
• 18^th/25^th February 2021
  • Introduction on using Intel Quartus and design compilations.
  • Registration details for HACK Club membership.

There will be a 48 hours design challenge which will be announced after the second session concludes on 25^th February 2021. Announcement of the results will be done through email.

Registration is compulsory for attending the workshop. Kindly fill this form for registering to the workshop.

Event Poster:

Resources

• Steps for solving assignments (iverilog, gtkwave) 0, 1, 2, and 3 link here.

• Theory material for assignment 6 and 7 link here.

• Steps for solving assignment (using quartus tool) 8 link here.